Dell PowerEdge R420 User Manual download pdf (Page 3)

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Item How is data input to this memory? How is this memory write protected?

Planer

PCH Internal CMOS RAM BIOS N/A – BIOS only control

BIOS SPI Flash SPI interface via iDRAC Software write protected

iDRAC SPI Flash SPI interface via iDRAC Embedded iDRAC subsystem firmware

actively controls sub area based write

protection as needed.

BMC EMMC NAND Flash interface via iDRAC Embedded FW write protected

CPU Vcore and VSA

Regulators

Once value are loaded into register

space a cmd writes to nvm.

There are passwords for different sections of

the register space

System CPLD RAM Not utilized Not accessible

System Memory System OS OS Control

Power Supplies

PSU FW Different vendors have different

utilities and tools to load the data to

memory. It can also be loaded by

Dell Update Package from LC or OS

(Windows and Linux)

Protected by the embedded microcontroller.

Special keys are used by special vendor

provided utilities to unlock the ROM with

various CRC checks during load.

4x3.5" Backplane

SEP internal flash I2C interface via iDRAC Program write protect bit

8x2.5" Backplane

SEP internal flash I2C interface via iDRAC Program write protect bit

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NOTE:

For any information that you may need, direct your questions to your Dell Marketing contact.

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Trademarks used in this text: Dell™, the DELL logo, and PowerEdge™ are trademarks of Dell Inc.

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Dell PowerEdge R420 User Manual Page 3